module Hazard_Det (
    input wire jump,
    input wire [4:0] ID_rs1,
    input wire [4:0] ID_rs2,
    input wire ID_rs1_use,
    input wire ID_rs2_use,
    input wire [4:0] EX_RF_waddr,
    input wire EX_rf_we,
    input wire [4:0] MEM_RF_waddr,
    input wire MEM_rf_we,
    input wire [4:0] WB_RF_waddr,
    input wire WB_rf_we,
    
    output wire stall,
    output wire flush//当收到EX阶段的jump时，flush分别给PC、和前两个流水寄存器
);


assign flush = jump;

wire RAW_A;
wire RAW_B;
wire RAW_C;



assign RAW_A = ((EX_RF_waddr == ID_rs1)&EX_rf_we & ID_rs1_use & (ID_rs1 != 5'b0))|((EX_RF_waddr == ID_rs2)&EX_rf_we & ID_rs2_use & (ID_rs2 != 5'b0));
assign RAW_B = ((MEM_RF_waddr == ID_rs1)&MEM_rf_we & ID_rs1_use & (ID_rs1 != 5'b0))|((MEM_RF_waddr == ID_rs2)&MEM_rf_we & ID_rs2_use & (ID_rs2 != 5'b0));
assign RAW_C = ((WB_RF_waddr == ID_rs1)&WB_rf_we & ID_rs1_use & (ID_rs1 != 5'b0))|((WB_RF_waddr == ID_rs2)&WB_rf_we & ID_rs2_use & (ID_rs2 != 5'b0));


assign stall = (RAW_A|RAW_B|RAW_C);    

endmodule